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Publications

 
ASPLOS 2021 (to appear) Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search
Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher
IEEE MICRO May-June 2020
(Top Picks of 2019)
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar
MICRO 2019 Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna
ISPASS 2019 Timeloop: A Systematic Approach to DNN Accelerator Evaluation
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer
ISCA 2017 SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
ACM Transactions on
Computer Systems,
September 2015
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy Allmon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer
IEEE Micro May-June 2014
(Top Picks of 2013)
Efficient Spatial Processing Element Control via Triggered Instructions
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, Joel Emer
ISCA 2013 Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, Joel Emer
FPGA 2012 Leveraging Latency-Insensitivity to Ease Multiple FPGA Design
Kermin Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel Emer
FPGA 2011 LEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic
Michael Adler, Kermin E. Fleming, Angshuman Parashar, Michael Pellauer, Joel Emer
HPCA 2011 HAsim: FPGA-Based High-Detail Multicore Simulation Using Time-Division Multiplexing
Michael Pellauer, Michael Adler, Michel Kinsy, Angshuman Parashar, Joel Emer
MIT CSAIL TR 2011 LEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic [Extended Version]
Michael Adler, Kermin E. Fleming, Angshuman Parashar, Michael Pellauer, Joel Emer
CARL 2010 LEAP: A Virtual Platform Architecture for FPGAs
Angshuman Parashar, Michael Adler, Kermin Fleming, Michael Pellauer, Joel Emer
SAW 2010 Using Reconfigurable Logic to replace Fixed-Function Blocks in SoCs
Tao Wang, Peng Li, Yuan Liu, Zhiyuan Zhang, Angshuman Parashar, Azam Barkatullah, Dong Liu, Joel S. Emer
NDCA 2009 Reconfigurable Logic: The Future Direction of Computer Architecture
Joel S. Emer, Angshuman Parashar, Tao Wang, and Azam Barkatullah
WARP 2008 Hybrid CPU/FPGA Performance Models
Angshuman Parashar, Michael Adler, Michael Pellauer, Joel Emer
ISCA 2007 Mechanisms for Bounding Vulnerabilities of Processor Structures
Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam
ASPLOS 2006 SlicK: Slice-Based Locality Exploitation for Efficient Redundant Multithreading
Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam
HPCRI 2005 SOS: Using Speculation for Memory Error Detection
Sudhanva Gurumurthi, Angshuman Parashar, Anand Sivasubramaniam
ISCA 2004 A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy
Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam