{"id":5,"date":"2010-08-15T21:09:41","date_gmt":"2010-08-16T01:09:41","guid":{"rendered":"http:\/\/www.parashar.org\/?page_id=5"},"modified":"2020-12-01T14:59:08","modified_gmt":"2020-12-01T19:59:08","slug":"publications","status":"publish","type":"page","link":"https:\/\/www.parashar.org\/?page_id=5","title":{"rendered":"Publications"},"content":{"rendered":"

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ASPLOS 2021 (to appear)<\/td>\nMind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search<\/a>
\nKartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W. Fletcher<\/td>\n<\/tr>\n
IEEE MICRO May-June 2020
\n(Top Picks of 2019)<\/td>\n		MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings<\/a>
\nHyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar<\/td>\n<\/tr>\n
MICRO 2019<\/td>\nUnderstanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach<\/a>
\nHyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna<\/td>\n<\/tr>\n
ISPASS 2019<\/td>\nTimeloop: A Systematic Approach to DNN Accelerator Evaluation<\/a>
\nAngshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel Emer<\/td>\n<\/tr>\n
ISCA 2017<\/td>\nSCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks<\/a>
\nAngshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally<\/td>\n<\/tr>\n
ACM Transactions on
\nComputer Systems,
\nSeptember 2015<\/td>\n		Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures<\/a>
\nMichael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy Allmon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer<\/td>\n<\/tr>\n
IEEE Micro May-June 2014
\n(Top Picks of 2013)<\/td>\n		Efficient Spatial Processing Element Control via Triggered Instructions<\/a>
\nAngshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, Joel Emer<\/td>\n<\/tr>\n
ISCA 2013<\/td>\nTriggered Instructions: A Control Paradigm for Spatially-Programmed Architectures<\/a>
\nAngshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen Maresh, Joel Emer<\/td>\n<\/tr>\n
FPGA 2012<\/td>\nLeveraging Latency-Insensitivity to Ease Multiple FPGA Design<\/a>
\nKermin Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel Emer<\/td>\n<\/tr>\n
FPGA 2011<\/td>\nLEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic<\/a>
\nMichael Adler, Kermin E. Fleming, Angshuman Parashar, Michael Pellauer, Joel Emer<\/td>\n<\/tr>\n
HPCA 2011<\/td>\nHAsim: FPGA-Based High-Detail Multicore Simulation Using Time-Division Multiplexing<\/a>
\nMichael Pellauer, Michael Adler, Michel Kinsy, Angshuman Parashar, Joel Emer<\/td>\n<\/tr>\n
MIT CSAIL TR 2011<\/td>\nLEAP Scratchpads: Automatic Memory and Cache Management for Reconfigurable Logic [Extended Version]<\/a>
\nMichael Adler, Kermin E. Fleming, Angshuman Parashar, Michael Pellauer, Joel Emer<\/td>\n<\/tr>\n
CARL 2010<\/td>\nLEAP: A Virtual Platform Architecture for FPGAs<\/a>
\nAngshuman Parashar, Michael Adler, Kermin Fleming, Michael Pellauer, Joel Emer<\/td>\n<\/tr>\n
SAW 2010<\/td>\nUsing Reconfigurable Logic to replace Fixed-Function Blocks in SoCs<\/a>
\nTao Wang, Peng Li, Yuan Liu, Zhiyuan Zhang, Angshuman Parashar, Azam Barkatullah, Dong Liu, Joel S. Emer<\/td>\n<\/tr>\n
NDCA 2009<\/td>\nReconfigurable Logic: The Future Direction of Computer Architecture<\/a>
\nJoel S. Emer, Angshuman Parashar, Tao Wang, and Azam Barkatullah<\/td>\n<\/tr>\n
WARP 2008<\/td>\nHybrid CPU\/FPGA Performance Models<\/a>
\nAngshuman Parashar, Michael Adler, Michael Pellauer, Joel Emer<\/td>\n<\/tr>\n
ISCA 2007<\/td>\nMechanisms for Bounding Vulnerabilities of Processor Structures<\/a>
\nNiranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam
\n<\/td>\n<\/tr>\n
ASPLOS 2006<\/td>\nSlicK: Slice-Based Locality Exploitation for Efficient Redundant Multithreading<\/a>
\nAngshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam
\n<\/td>\n<\/tr>\n
HPCRI 2005<\/td>\nSOS: Using Speculation for Memory Error Detection<\/a>
\nSudhanva Gurumurthi, Angshuman Parashar, Anand Sivasubramaniam
\n<\/td>\n<\/tr>\n
ISCA 2004<\/td>\nA Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy<\/a>
\nAngshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam
\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

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\u00c2\u00a0 ASPLOS 2021 (to appear) Mind Mappings: Enabling Efficient Algorithm-Accelerator Mapping Space Search Kartik Hegde, Po-An Tsai, Sitao Huang, Vikas Chandra, Angshuman Parashar, Christopher W.…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-5","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.parashar.org\/index.php?rest_route=\/wp\/v2\/pages\/5","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.parashar.org\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.parashar.org\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.parashar.org\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.parashar.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=5"}],"version-history":[{"count":0,"href":"https:\/\/www.parashar.org\/index.php?rest_route=\/wp\/v2\/pages\/5\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.parashar.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=5"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}